C8051F850 Low Power Operation

Contents

Introduction

The following documents the results of low power tests performed on a C8051F850 (850) processor. For testing, a MINT board was modified to eliminate the 3.3 Volt regulator and the "PWR" indicator LED. The modified board was mounted on a MINT development platform consisting of a socket for the MINT board and screw-down terminals for I/O connections.

Schematic 1 shows the MINT modifications, development board connections and interface to the BOBI board for programming. Application Note 8 describes the BOBI interface in more detail.

Power Measurement

Power consumption was measured by inserting a 100 Ohm resistor in series with the MINT power connection. In Schematic 1 this resistor is designated R5. The actual value of R5, 99.29 Ohms, was measured with an Agilent 34410A multimeter and is used for all calculations.

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Power Measurement (Cont.)

The voltage drop across R5, divided by its value determines the current consumption of the processor. The test voltage was applied to R5 with a BK Precision 9110 adjustable power supply. The voltage was adjusted to as near as possible to 3 Volts.

Because power can feed from the MIDE programmer board to the test board, the BOBI board was disconnected prior to performing all measurements.

Power reduction was performed solely by reducing the 850's clock speed by using the internal low frequency oscillator and further reducing consumption by dividing this oscillator down before being used as the system clock (SYSCLK). Other methods, such as using the idle and stop modes, may result in additional power savings but these are more complicated to implement and were not tried. Analog peripherals, such as the A/D converter and programmable counter array, were disabled for all tests.

To verify that the processor was functional, a port pin was toggled and monitored on an oscilloscope. This signal was generated by a tight "main" loop, as described in the software section below.

Photo 1 shows the MINT board mounted on a development board and connected to the programmer via a BOBI interface. The instrumentation, MIDE programmer and current measurement resistor are not shown.

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Figure 1 shows the chip initialization performed to reduce power consumption.

     117	:m -int   [ 7 .IE clr ] m;   :m +int   [ 7 .IE set ] m;
     118	\
     119	-: ?OSCLCN  OSCLCN #@  6 .T if. drop ; then drop ?OSCLCN ;
     120	\  
     121	-: /chip  \ initialize chip
     122 \
     123	\ -----[ disable watchdog ]
     124	\ 
     125	   -int
     126	   $de # WDTCN #!    $ad # WDTCN #!  \ disable watchdog
     127	\ 
     128	\ -----[ enable LF clock ]
     129	\ 
     130	   $80 # OSCLCN #!   ?OSCLCN  \ enable LF clock/8, stabilize
     131	\ 
     132	\ -----[ select clock source ]
     133	\ 
     134	\   $00 # CLKSEL #!    \ internal 24.5 MHz osc., SYSCLK/1  150315rjn
     135	\   $02 # CLKSEL #!    \  LF clock/8, SYSCLK/1  150315rjn
     136	\   $32 # CLKSEL #!    \ LF clock/8, SYSCLK/8   150315rjn
     137	   $72 # CLKSEL #!   \ LF  clock/8, SYSCLK/128  150315rjn
     138	\ 
     139	\ -----[ configure I/O ] 
     140	\ 
     141	   $00 # XBR2 #!     \ disable xbr	
     142	\   $f0 # ADC0PWR #! \ makes no difference for low power	 
     143	\ ----- port 0                
     144	   $ff # P0MDOUT #!  \ all push/pull outputs	
     145	\ ----- port 1
     146	   $ff # P1MDOUT #!  \ all PP outputs
     147	\ ----- port2   
     148	   $fe # P2MDOUT #!  \ P2[0] DI -- C2D
     149	   $00 # XBR1 #!        \ no resources routed to port pins (default)
     150	   $40 # XBR2 #!   ;    \ enable XBR, weak pullups
       

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Initialization (Cont.)

Line 119 defines ?OSCLCN to check that the low frequency clock is stabilized. This is performed by verifying that bit 6 of the OSCLCN register is set. If this bit is not set, the word loops until it is. The initial code for low power operation did not have this check and appeared to work reliably. It was included primarily to be politically correct.

Line 130 sets bit 7 in the OSCLCN register to enable the low power oscillator and then uses ?OSCLCN to check that it is stable before selecting it as a clock source. The lower two bits of OSCLCN set the low frequency clock rate. In this code, the rate is set to the lowest value: divide by 8. Thus, the nominal 80 kHz rate of the low frequency clock is divided down to 10 kHz.

Lines 131 to 137 set the CLKSEL register to select the low frequency internal oscillator and the SYSCLK divisor rate. With the lowest divisor of 128, the SYSCLK rate is approximately (10 kHz)/128 = 78.125 Hertz.

Lines 139 to 150 configure the chip I/O. In this case, most port pins are set to outputs and no system resources are routed to port pins. Note that the system clock can be routed to a port pin (e.g., P0.0) to check the actual clock frequency. This was not done for the low power tests because the frequency could easily be calculated from the period of the output signal and instruction timing.

Figure 2 shows the definition of the word alive that generates the square wave output on P0.1. Note the use of alive in the turnkey startup word, go.

  1	:m alive  [ 1 .p0 toggle ] m;  \ generates "alive" signal
  2  \ 
  3	-: go  /chip  begin alive again  \ turnkey startup word
         

Line 1 is a macro that toggles port 0, pin 1.

Line 3 defines the turnkey startup word, go. The startup word first executes /chip to initialize the chip. The initialization word is defined in Figure 1, above. After initialization, the program enters an infinite loop that repeatedly executes alive, defined in Line 1, to toggle P0.1.

The signal on P0.1 is used to show that the processor is operating and to generate a square wave that can be used to determine the system clock rate. The following sections show clock rate calculations.

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Test Results

Figure 3 provides a summary of the above test results.

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Revision Summary

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