DECL PLL Multiplier & Decade Divider Module

PRODUCT INDEX

• Introduction
• Features and Specifications
• Physical
• Outputs
• Design, Operation and Test
• Design
• Operation
• Test
• Input
• Outputs
• Power
• Polarity
• Connections
• Voltage
• Current
• Dissipation
• Parts List
• Revision Summary

Page 2

Introduction

The following describes the design, construction, operation and use of the DECL (Decade PLL) module. The module has both a Phase Locked Loop (PLL) frequency multiplier and a frequency divider to produce various output frequencies that are based on an input reference frequency. The primary use of the module is to condition the ten megahertz (10 MHz) signal from a reference oscillator and produce divided and multiplied outputs synchronized to the reference.

The DECL module uses two chips, a PLL chip and a microprocessor chip, to convert the rubidium input signal to a logic level and multiply and divide that signal to provide multiple frequency outputs that are related to the reference.

Photo 1 shows a top view of the module and Photo 2 shows the bottom view.

PLL

The PLL chip conditions the input signal to provide a buffered, logic-level output. This output also drives the microprocessor clock input. The PLL provides a multiplied output, typically 25 MHz, for use as a stable phase-locked output that is derived from the input reference frequency.

Microprocessor

The microprocessor takes the buffered output of the reference signal and divides it to produce marker signals at various frequencies from 1 MHz to 1 Hertz. The microprocessor and its code are the same as used for the DECUS decade divider module.

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Features and Specifications

For the following, refer to the Schematic 1 titled "DECL MODULE -- DECUS WITH PLL FRONT END."

You can also download DECL schematics in a zip file.

The schematic shows the components, circuitry and some operational information for the module. For example, the schematic includes a table for PLL jumper options and bottom-side component placement for the DECL PC Board. The Parts List provides additional information about the components used to assemble the module.

As shown in Photo 1, the module measures approximately 1 1/4 by 7/8 inches (32 by 23 mm). This is the same size as the the DECUS module. Signal connections are provided on two 12-pin single-row pin headers. The header connections are labeled "A" to "X" for easy reference.

The connections are also labeled according to function (e.g., "06" for P0.6). Header pins are spaced one tenth of an inch apart and the header rows are spaced 0.6 inch apart. This allows the module to be used with breadboard sockets or wired with in-line sockets on a prototyping board. Note that the inter-pin capacitance of breadboarding sockets can distort some higher frequency outputs, especially PLL outputs with higher multipliers (e.g., 5).

The module provides nine different divider outputs, ranging from one Hertz to one megahertz (MHz). The module also provides a 10 MHz conditioned output and a frequency-multiplied outptut from the PLL chip. The multiplied output is 33.33 MHz when the option pins are left open (factory default). Users will typically want to wire option pins "O" and "P" high to produce a 25 MHz reference output.

With a 10 MHz input from a frequency reference, the multiplied output can range from 20 MHz (2X) to 50 MHz (5X) by wiring the option pins "O" and "P" according to the PLL Multiplier table in the schematic.

The DECL module includes a footprint for a P-channel MOSFET that can be wired to drive an LED. For example this can be used to indicate that a rubidium reference source is locked. As shown in Schematic 1, the LED drive connects to the MOSFET gate at module pin "K" (BIT) and the indicator LED connects between module pin "M" and ground (in "R"). Pin "N" (LOC) must also be wired to the power supply input voltage.

A footprint for a LED current limit resistor, R5, is provided on the module. This is typically 180 Ohms to provide approximately 10 milliamperes through a red LED (assuming a 5 Volt module input). The location of this resistor is marked on the schematic's component placement diagram so that it can be easily identified and adjusted.

The divider outputs are driven by microprocessor port pins capable of sourcing or sinking up to 100 milliamperes (100 mA) each. Thus, the one Hertz output can directly drive an LED to act as an "active" indicator. These drive capabilities are limited by the choice of input voltage and the current limitations of the regulator, as noted in the Power section. The output of the PLL can drive up to 25 milliamperes, also subject to the limitations of the voltage regulator.

Page 4

Design, Operation and Test

To set up the module for operation, it is necessary only to supply it with power and an input signal. Once set up for operation, outputs are continuously available at the lettered output pins, as indicated in Schematic 1.

The following sections describe power and signal requirements, module connections and test procedures.

Page 5

Photo 3 shows the DECL test platform used to test DECL modules.

Like the AGEN test platform, the base is made with a weighted breath mint tin. The tin is filled with junk hardware and coated on the bottom with E6000 glue to make a heavy, slide-resistant base. The test platform circuitry is wired on a protoboard originally designed for microprocessor development. The protobard was trimmed to fit the base and two mounting holes were drilled to allow mounting the board on standoffs. The board is fastened to the base with four hermaphroditic standoffs. The screw ends of the standoffs face up and the board fits over them. The board is held to the base with nylon standoffs screwed on two of the standoff ends.

Paper labels glued next to major components help identify main features of the platform. For example, the "RI" label on the BNC connector indicates the "reference input" from the oscillator.

As shown in Schematic 2, the test platform brings the outputs to a 10-pin single row header. One pin is dedicated to each of the nine output frequencies. Pin 10 is wired to the input voltage so that it can be checked with a voltmeter or scope. The row of output pins is labeled "outputs" in photo 3. Another row of stake pins provides ground connections for scope and voltmeter probes. Where pin indication in necessary, pin 1 of each connector or row of pins is marked with a dab of white paint.

The input from the rubidium reference is connected via a 2X5 shrouded IDC plug; the mating socket and ribbon cable connects to a chassis-mount BNC connector glued to the base. This provides a solid connection for the BNC-terminated cable from the reference while allowing the board to be disconnected from the base for wiring and modifications.

A polarized power connector (labeled "5V") provide 5 Volt power and a green indicator LED (not labeled) provides positive indication that power is applied to the module.

A second red LED connects to the lock indicator P-channel MOSFET as an activity indicator. The FET is driven from the 1 Hertz output so that the red LED flashes when the output is active. This also provides a positive indication that the input signal is present and that the lock indicator FET and the its current limiter are wired correctly.

A table of jumper settings for various multiplication options was cut from the test platform schematic and pasted on the base (not visible) to provide a convenient reference during testing.

Page 6

Input

The input signal is applied between the module pins labeled "J" (RI) and "C" (ground), as shown in Schematic 1. The conditioning circuit is designed to be compatible with the LPRO-101 specifications with a typical input signal of 0.55 Volts RMS (approximately 1.5 Volts p-p). DECUS Photo 1 shows the typical input conditioning signals for a LPRO input.

Note: The input may not operate reliably for signal inputs under one Volt peak to peak. Inputs as high as 6 Volts peak to peak have been used but are not recommended for routine operation.

To verify the correct operation of the conditioning circuit, use an oscilloscope to observe the input signal between ground and pin "U" (0.3) of the module. If the input voltage is within the range specified above, a 10 MHz square wave should be present. Also, with no jumpers installed at pins "O" and "P", a 33.33 MHz signal should appear at pin "S" (PLL).

Page 7

Outputs

The DECL output frequencies and module pins are:

Page 8

Power

The module is not protected against input voltage reversal. Take care to verify that the correct voltage polarity is applied to the power input pins.

Revision Summary